Evaluation and measurement of the wordline to bitline delay is important in the design and manufacture of semiconductor static random access memory (SRAM) cells. The wordline to bitline delay is a part of the read access path delay in any array memory unit. It is important to properly evaluate the delay in order to determine the length of the critical path. Over estimation of the delay implies a too slow clock frequency, while under estimation may cause logical failures.
Existing methods for measuring this delay are complex, and hence the design of latch-based circuits is typically based on simulations. Testing the stability of cells is typically performed using customized test patterns, but it is difficult to interpret failures, as numerous other factors are at play. Thus, it has been difficult to measure on-chip wordline to bitline delay due to: (1) the difficulty in producing a precise delay at high frequencies; and (2) the difficulty in delivering the phases of clock and data to the SRAM cell within a chip because the probe/pad/line/connector delay is very complex to control and predict.
One common prior art technique for measuring this delay includes measuring the delay off-chip using precise waveform generators and oscilloscopes which relies on use of precision probes, cables and connectors. This technique requires costly equipment and is difficult to do in practice.
Another technique measures the delay using on-chip counters and delay lines. This requires the significant addition of circuitry to the layout, thus costing precious chip real estate. Yet another technique utilizes a ring oscillator, but with a modified version of the actual SRAM cell. This technique requires modification of the SRAM cell to include one or more logic gates within the cell itself which are required for the ring oscillator to oscillate. Thus, the SRAM cell under test is not the real world cell, but a modified one.
Other techniques use a ring oscillator, but with a special organization of the array that affects the behavior of the cell with respect to the real array organization.
There is thus a need for a circuit and related technique for measuring the wordline to bitline delay (i.e. the read access time) of an SRAM cell and to evaluate its stability in situ (i.e. while operating in a realistic environment) and without requiring the probing of any cells, or estimating the delay in a static manner, or where the cell is required to be modified from its real world operating configuration.